ARES PCB Layout Software Our high performance netlist based PCB design package perfectly complements our powerful ISIS schematic capture software and features both automatic component placement and a highly effective Rip-Up and Retry auto-router. ISIS and ARES together form a complete Proteus PCB Design package. The following features are provided by ARES: 16 copper layers, 2 silk screen layers, 4 mechanical layers plus board edge, keepout, solder resist and solder paste mask. Any angle component placement. Padstacks - different pad shapes on each layer. Circular, Square, DIL, Finger and polygonal pad shapes. Advanced route editing features including Topological Route Editing, Auto Track Necking and easy to use curved trace support. Package libraries include both SMT and THP parts, over 1000 packages in total. User definable snap grids and Real Time Snap to deal with tricky SMT pin spacings. Advanced Netlist Management provides for painless design modifications including pin-swap/gate-swap and back-annotation to the ISIS schematic capture software. Different track and via sizes, layers and physical design rules can be specified for different groups of nets using routing strategies. Ratsnest display and Force Vectors displays - both updated in real time. Connectivity and Design Rule checkers. Gridless polygonal power planes. Output via any Windows device driver, also Gerber, Excellon and DXF formats. Gerber Viewer with Panelization/Tiling facility. Gerber Import Tool for importing designs from other PCB packages. Design Automation: Automatic Component Placement. A fast and configurable auto-placer is available that will place components on to a given board with optimum position, spacing and orientation. Multi-strategy grid based auto-routing. Special routines handle SMT parts. Rip-Up & Retry for 100% routing on most boards. Tidy pass reduces via count and track length. Screen shot of ARES showing detail of a two layer board. The top layer is in red, the bottom layer in blue. Where objects on the two layers overlap, they appear in magenta (red plus blue) so that items on the top layer never obscure items on the bottom layer. Schematic Entry Schematic entry of the design is done using our ISIS schematic capture software. Which is able to generate netlists and transfer them directly in to ARES as a single seamless operation so allowing you to start new layouts or update existing layouts with ease. Any design modifications to the layout (re-annotation, pin-swaps or gate-swaps) are seamlessly transferred back to the schematic when you next switch back to ISIS or re-load the schematic design. Although ISIS is included as standard with all Proteus PCB Layout packages, ARES is also able to work from third-party schematic capture packages providing they can produce netlists in either Tango or Multiwire format. However, back-annotation to such packages is not supported. Layout Database ARES features a state of the art layout database capable of representing the most complex of PCB designs. Placement resolution is 10 nanometers within a maximum board size of 20m. Components and other objects may be rotated in 0.1 degree increments whilst padstacks facilitate the achievement of maximum routing area on inner layers. Route Editing Topological route editing allows you to re-route or delete any section of a track, irrespective of how it was originally placed. Commands are also provided to change the thickness and/or layer of any section of tracking. If thick tracks are laid between obstacles such as IC pads, ARES will automatically insert a narrower 'neck' in order to maintain the current design rules. Curved tracks can be laid down simply by pressing the CTRL key and marking the route with the mouse. Package Libraries The supplied libraries cover a large range of through hole components including all the most common IC, transistor, diode and connector packaging types. We also supply as standard libraries for both discrete and IC SMT footprints; the latter including SOP, SOJ, PLCC, CLCC, QFP and PQFP types. New packages can be created directly on the drawing whilst ARES also supports general 2D drafting features. Netlist Handling During the placement phase, ARES displays both the ratsnest and force vectors. Both are updated in real time when you drag components. The ratsnest is also automatically updated during routing - add a track and a ratsnest line will disappear; delete a track and one will re-appear. The system fully supports design modifications - if you change the schematic and re-load the netlist, ARES will flag up exactly which components and/or tracks are affected. Equally, pin-swaps and gate-swaps made in ARES are automatically fed back to the schematic. Auto Placer Automatic component placement makes it possible to design an entire board with absolute minimum of effort on your part. Alternatively, since the placer can operate interactively, you can pre-place critical components first and then let ARES auto-place the rest. Autorouting Our grid based router is both flexible and fast and can route using any track thickness or via width, at 90 or 45 degrees, and on 1-8 layers. It was placed in the top Category A in the recent review of PCB software (Electronics & Wireless World magazine, January 1997). The range of routing grids available enables you to trade off routing density against execution speed with densities of 1, 2 or 3 traces between IC pads. The router also has special routines which enable it to form 'fan outs' from rows of SMT pads which would otherwise be off grid, thus enabling it to perform well with boards containing SMT parts. The Rip-Up and Retry mode enables it to remove and replace tracks which block others giving 100% completion on most medium density boards routed at 50 or 25 thou. Meanwhile, our innovative costing/scheduling logic reduces the via count by as much as four fold over low-medium cost routers. Finally, you can run the tidy pass which reduces both track length and via count whilst improving the aesthetic quality of your board at the same time. Routing with ELECTRA For customers looking for the very latest in autorouting technology we have provided an integrated bi-directional interface to the ELECTRA autorouter. This router uses adaptive shape based autorouting algorithms to achieve completion, often surpassing industry standard benchmarks. More information on ELECTRA, links to a trial download and pricing can be found here. Power Planes ARES features the ultimate in power plane support - user placeable polygonal regions within which inner boundaries are automatically created around existing pads and tracking. Change the pads and tracking and the boundaries are recomputed to maintain design rule clearances. Thermal reliefs are supported and you can choose whether to hatch or fill each polygon. All computation is based on grid-less shape geometry and occurs in the background so that there is interference in manual board placement for computationally intensive layouts. Close up of two ARES zones with the same board. The top-left shows a hatched zone with thermally relieved connections whilst the lower-right shows a solid zone with solid, unrelieved, connections. Design Rule Checking During manual routing, ARES checks each track as you place it and warns you if any design rules (physical/electrical) are broken. You can also run global physical and electrical design rule checks at any time. The latter produces a report listing any missing or extra connections - double click on any entry in the list, and ARES will zoom in to show you exactly where the error is located on the PCB. "I just had to send a quick note to let you know how impressed I am with the Zone feature. After about a five minute learning curve I was off, making a solid, and then hatched, ground plane. Everything works as advertised, including minimum zone width, edging on hatches, etc." - Customer Testimonial. "Proteus really shines in automating the difficult tasks, to the point of allowing me to consider doing a high-precision analog front end on a 2-layer card." - Customer Testimonial.